In designing a semiconductor integrated circuit (hereinafter called a “large-scale integrated circuit (LSI)”), resistance and capacitance (RC) extraction within the circuit is conducted based on layout information of a designed circuit, and the layout information of the circuit is corrected in a case where it is determined that timing constraint is not satisfied by the RC extracted result. The RC extraction is conducted using the corrected layout information after the correction of the layout information of the circuit.
To efficiently calculate a delay time associated with the layout correction, there is proposed a technology to partially calculate the delay time by acquiring wiring information affected by the layout correction, and extracting RC connection information merely associated with this acquired wiring information affected by the layout correction.